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| a FEATURES EASY TO USE Pin-Strappable Gains of 10 & 100 All Errors Specified for Total System Performance Higher Performance than Discrete In-Amp Designs Available in 8-Pin DIP and SOIC Low Power, 1.3 mA max Supply Current Wide Power Supply Range ( 2.3 V to 18 V) EXCELLENT DC PERFORMANCE 0.15% max, Total Gain Error 5 ppm/ C, Total Gain Drift 125 V max, Total Offset Voltage 1.0 V/ C max, Offset Voltage Drift LOW NOISE 9 nV/Hz, @ 1 kHz, Input Voltage Noise 0.28 V p-p Noise (0.1 Hz to 10 Hz} EXCELLENT AC SPECIFICATIONS 800 kHz Bandwidth (G = 10}, 200 kHz (G = 100} 12 s Settling Time to 0.01% APPLICATIONS Weigh Scales Transducer Interface & Data Acquisition Systems Industrial Process Controls Battery Powered and Portable Equipment PRODUCT DESCRIPTION Low Drift, Low Power Instrumentation Amplifier AD621 CONNECTION DIAGRAM 8-Pin Plastic Mini-DIP (N), Cerdip (Q) and SOIC (R) Packages G=10/100 -IN +IN -VS 1 2 3 4 AD621 8 7 6 5 G=10/100 +VS OUTPUT REF TOP VIEW pin strapping. The AD621 is fully specified as a total system, therefore, simplifying the design process. For portable or remote applications, where power dissipation, size and weight are critical, the AD621 features a very low supply current of 1.3 mA max and is packaged in a compact 8-pin SOIC, 8-pin plastic DIP or 8-pin cerdip. The AD621 also excels in applications requiring high total accuracy, such as precision data acquisition systems used in weigh scales and transducer interface circuits. Low maximum error specifications including nonlinearity of 10 ppm, gain drift of 5 ppm/C, 50 V offset voltage and 0.6 V/C offset drift ("B" grade), make possible total system performance at a lower cost than has been previously achieved with discrete designs or with other monolithic instrumentation amplifiers. When operating from high source impedances, as in ECG and blood pressure monitors, the AD621 features the ideal combination of low noise and low input bias currents. Voltage noise is specified as 9 nV/Hz at 1 kHz and 0.28 V p-p from 0.1 Hz to 10 Hz. Input current noise is also extremely low at 0.1 pA/Hz. The AD621 outperforms FET input devices with an input bias current specification of 1.5 nA max over the full industrial temperature range. 10,000 The AD621 is an easy to use, low cost, low power, high accuracy instrumentation amplifier which is ideally suited for a wide range of applications. Its unique combination of high performance, small size and low power, outperforms discrete in amp implementations. High functionality, low gain errors and low gain drift errors are achieved by the use of internal gain setting resistors. Fixed gains of 10 and 100 can be easily set via external 30,000 TOTAL ERROR, ppm OF FULL SCALE 20,000 3 - OP AMP IN-AMPS (3 OP 07'S) TOTAL INPUT VOLTAGE NOISE, G = 100 - Vp-p (0.1 - 10Hz) 25,000 1,000 TYPICAL STANDARD BIPOLAR INPUT IN-AMP 15,000 100 AD621A 10,000 10 AD621 SUPERETA BIPOLAR INPUT IN-AMP 5,000 1 0 5 10 SUPPLY CURRENT - mA 15 20 0.1 1k 10k 100k 1M 10M 100M SOURCE RESISTANCE - Three Op Amp IA Designs vs. AD621 Total Voltage Noise vs. Source Resistance REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD621-SPECIFICATIONS Gain = 10 (typical @ +25 C, V = S 15 V, and RL = 2 k , unless otherwise noted) Min AD621A Typ Max Min AD621B Typ Max Min AD620S1 Typ Max Units Model GAIN Gain Error Nonlinearity, VOUT = -10 V to +10 V Gain vs. Temperature TOTAL VOLTAGE OFFSET Offset (RTI) Over Temperature Average TC Offset Referred to the Input vs. Supply (PSR)2 Total NOISE Voltage Noise (RTI) RTI Current Noise INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC INPUT Input Impedance Differential Common-Mode Input Voltage Range3 Over Temperature Over Temperature Common-Mode Rejection Ratio DC to 60 Hz with 1 k Source Imbalance OUTPUT Output Swing Over Temperature Conditions VOUT = 10 V RL = 2 k 2 -1.5 75 1.0 95 120 13 0.55 100 10 0.5 3.0 0.3 1.5 0.15 10 5 250 400 2.5 100 17 2 -1.5 50 0.6 120 13 0.55 100 10 0.5 3.0 0.3 1.5 0.05 10 5 125 215 1.5 95 17 0.8 2 -1 75 1.0 120 13 0.55 100 10 0.5 8.0 0.3 8.0 0.15 10 5 250 500 2.5 % ppm of FS ppm/C V V V/C dB VS = 15 V VS = 5 V to 15 V VS = 5 V to 15 V VS = 2.3 V to 18 V 1 kHz 0.1 Hz to 10 Hz f = 1 kHz 0.1 Hz-10 Hz VS = 15 V 17 0.8 nV/Hz V p-p fA/Hz pA p-p nA nA pA/C nA nA pA/C 2.0 2.5 1.0 1.5 1.0 1.5 0.5 0.75 2 4 1.0 2.0 10 2 10 2 VS = 2.3 V to 5 V VS = 5 V to l8 V -VS + 1.9 -VS + 2.1 -VS + 1.9 -VS + 2.1 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.4 -VS + 1.9 -VS + 2.1 -VS + 1.9 -VS + 2.1 10 2 10 2 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.4 -VS + 1.9 -VS + 2.1 -VS + 1.9 -VS + 2.3 10 2 10 2 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.4 G pF G pF V V V V VCM = 0 V to 10 V RL = 10 k, VS = 2.3 V to 5 V VS = 5 V to 18 V 93 110 100 110 93 110 dB Over Temperature Short Current Circuit DYNAMIC RESPONSE Small Signal, -3 dB Bandwidth Slew Rate Settling Time to 0.01% REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance -VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 18 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5 -VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 18 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5 -VS + 1.1 -VS + 1.6 -VS + 1.2 -VS + 2.3 18 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5 V V V V mA 0.75 10 V Step 800 1.2 12 20 +50 0.75 800 1.2 12 20 +50 1 0.0001 0.75 800 1.2 12 20 +50 kHz V/s s k A V VIN +, VREF = 0 -VS + 1.6 1 0.0001 +60 +VS - 1.6 -VS + 1.6 +60 +VS - 1.6 VS + 1.6 +60 +VS - 1.6 1 0.0001 18 1.3 1.6 VS = 2.3 V to 18 V 2.3 0.9 1.1 -40 to +85 18 1.3 1.6 2.3 0.9 1.1 -40 to +85 18 1.3 1.6 2.3 0.9 1.1 V mA mA C -55 to +125 NOTES 1 See Analog Devices military data sheet for 883B tested specifications. 2 This is defined as the supply range over which PSRR is defined. 3 Input Voltage Range = CMV + (Gain x VDIFF). Specifications subject to change without notice. -2- REV. A AD621 Gain = 100 Model GAIN Gain Error Nonlinearity, VOUT = -10 V to +10 V Gain vs. Temperature TOTAL VOLTAGE OFFSET Offset (RTI) Over Temperature Average TC Offset Referred to the Input vs. Supply (PSR)2 Total NOISE Voltage Noise (RTI) RTI Current Noise INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC INPUT Input Impedance Differential Common-Mode Input Voltage Range3 Over Temperature Over Temperature Common-Mode Rejection Ratio DC to 60 Hz with 1 k Source Imbalance OUTPUT Output Swing Over Temperature VS = 5 V to 18 V Over Temperature Short Current Circuit DYNAMIC RESPONSE Small Signal, -3 dB Bandwidth Slew Rate Settling Time to 0.01% REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance (typical @ +25 C, VS = Conditions 15 V, and RL = 2 k , unless otherwise noted) Min AD621A Typ Max Min AD621B Typ Max Min AD620S1 Typ Max Units VOUT = 10 V RL = 2 k 2 -1 35 0.3 110 140 9 0.28 100 10 0.5 3.0 0.3 1.5 0.15 10 5 125 185 1.0 120 13 2 -1 25 0.1 140 9 0.28 100 10 0.5 3.0 0.3 1.5 0.05 10 5 50 215 0.6 110 13 0.4 2 -1 35 0.3 140 9 0.28 100 10 0.5 8.0 0.3 8.0 0.15 10 5 125 225 1.0 % ppm of FS ppm/C V V V/C dB VS = 15 V VS = 5 V to 15 V VS = 5 V to 15 V VS = 2.3 V to 18 V 1 kHz 0.1 Hz to 10 Hz f = 1 kHz 0.1 Hz-10 Hz VS = 15 V 13 0.4 nV/Hz V p-p fA/Hz pA p-p nA nA pA/C nA nA pA/C 2.0 2.5 1.0 1.5 1.0 1.5 0.5 0.75 2 4 1.0 2.0 10 2 10 2 VS = 2.3 V to 5 V VS = 5 V to l8 V -VS + 1.9 -VS + 2.1 -VS + 1.9 -VS + 2.1 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.4 -VS + 1.9 -VS + 2.1 -VS + 1.9 -VS + 2.1 10 2 10 2 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.4 -VS + 1.9 -VS + 2.1 -VS + 1.9 -VS + 2.3 10 2 10 2 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.4 G pF G pF V V V V VCM = 0 V to 10 V RL = 10 k, VS = 2.3 V to 5 V 110 130 120 130 110 130 dB -VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 18 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5 -VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 18 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5 -VS + 1.1 -VS + 1.6 -VS + 1.2 -VS + 2.3 18 +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5 V V V V mA 0.75 10 V Step 200 1.2 12 20 +50 0.75 200 1.2 12 20 +50 1 0.0001 0.75 200 1.2 12 20 +50 kHz V/s s k A V VIN +, VREF = 0 -VS + 1.6 1 0.0001 +60 +VS - 1.6 -VS + 1.6 +60 +VS - 1.6 VS + 1.6 +60 +VS - 1.6 1 0.0001 18 1.3 1.6 VS = 2.3 V to 18 V 2.3 0.9 1.1 -40 to +85 18 1.3 1.6 2.3 0.9 1.1 -40 to +85 18 1.3 1.6 2.3 0.9 1.1 V mA mA C -55 to +125 NOTES 1 See Analog Devices military data sheet for 883B tested specifications. 2 This is defined as the supply range over which PSEE is defined. 3 Input Voltage Range = CMV + (Gain x VDIFF). Specifications subject to change without notice. REV. A -3- AD621 ABSOLUTE MAXIMUM RATINGS 1 ESD SUSCEPTIBILITY Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 650 mW Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 25 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range (Q) . . . . . . . . . . -65C to +150C Storage Temperature Range (N, R) . . . . . . . . -65C to +125C Operating Temperature Range AD621 (A, B) . . . . . . . . . . . . . . . . . . . . . . -40C to +85C AD621 (S) . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature Range (Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300C NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Pin Plastic Package: JA = 95C/Watt 8-Pin Cerdip Package: JA = 110C/Watt 8-Pin SOIC Package: JA = 155C/Watt ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. Although the AD621 features proprietary ESD protection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. ORDERING GUIDE Temperature Range - 40C to +85C - 40C to +85C - 40C to +85C - 40C to +85C - 55C to +125C -40C to +85C Package Description 8-Pin Plastic DIP 8-Pin Plastic DIP 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Cerdip Package Option1 N-8 N-8 R-8 R-8 Q-8 Model AD621AN AD621BN AD621AR AD621BR AD621SQ/883B2 AD621ACHIPS Die NOTES 1 N = Plastic DIP; Q = Cerdip; R = SOIC. 2 See Analog Devices' military data sheet for 883B specifications. METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). Contact factory for latest dimensions. -4- REV. A Typical Characteristics-AD621 50 SAMPLE SIZE = 90 40 PERCENTAGE OF UNITS PERCENTAGE OF UNITS 40 50 SAMPLE SIZE = 90 30 30 20 20 10 10 0 -200 -100 0 +100 INPUT OFFSET VOLTAGE - V +200 0 -800 -400 0 +400 INPUT BIAS CURRENT - pA +800 Figure 1. Typical Distribution of VOS, Gain = 10 Figure 4. Typical Distribution of Input Bias Current 50 CHANGE IN OFFSET VOLTAGE - V 2 SAMPLE SIZE = 90 40 PERCENTAGE OF UNITS 1.5 30 1 20 0.5 10 0 -80 -40 0 +40 INPUT OFFSET VOLTAGE - V +80 0 0 1 2 3 WARM-UP TIME - Minutes 4 5 Figure 2. Typical Distribution of VOS, Gain = 100 Figure 5. Change in Input Offset Voltage vs. Warm-Up Time 50 SAMPLE SIZE = 90 1000 PERCENTAGE OF UNITS VOLTAGE NOISE - nV/Hz 40 100 GAIN = 10 30 20 10 10 GAIN = 100 0 -400 -200 0 +200 INPUT OFFSET CURRENT - pA +400 1 1 10 100 1k 10k 100k FREQUENCY - Hz Figure 3. Typical Distribution of Input Offset Current Figure 6. Voltage Noise Spectral Density REV. A -5- AD621 1000 100mV 100 1s CURRENT NOISE - fA/ Hz 90 100 10 0% 10 1 10 100 FREQUENCY - Hz 1000 Figure 7. Current Noise Spectral Density vs. Frequency Figure 9. 0.1 Hz to 10 Hz Current Noise, 5 pA per Vertical Div, 1 Second per Horizontal Div 100,000 TOTAL DRIFT FROM 25C TO 85C, RTI - V RTI NOISE - 0.2 V/div 10,000 FET INPUT IN-AMP 1000 100 AD621A 10 1k 10k 100k 1M SOURCE RESISTANCE - 10M TIME - 1 sec/div Figure 8a. 0.1 Hz to 10 Hz RTI Voltage Noise, Gain = 10 Figure 10. Total Drift vs. Source Resistance +160 +140 +120 RTI NOISE - 0.1 V/div GAIN = 100 CMR - dB +100 +80 +60 +40 +20 0 0.1 GAIN = 10 TIME - 1 sec/div 1 10 100 1k 10k 100k 1M FREQUENCY - Hz Figure 8b. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100 Figure 11. CMR vs. Frequency, RTI, for a Zero to 1 k Source Imbalance -6- REV. A AD621 180 160 G = 100 140 120 35 G = 10 & 100 30 OUTPUT VOLTAGE - Volts p-p 10k 100k 1M 25 PSR - dB G = 10 100 80 60 40 20 0.1 20 15 10 5 0 1 10 100 1k FREQUENCY - Hz 1k 10k 100k 1M FREQUENCY - Hz Figure 12. Positive PSR vs. Frequency Figure 15. Large Signal Frequency Response 180 160 G = 100 140 120 +Vs -0.0 INPUT VOLTAGE LIMIT - Volts (REFERRED TO SUPPLY VOLTAGES) -0.5 -1.0 -1.5 PSR - dB G = 10 100 80 60 40 20 0.1 +1.5 +1.0 +0.5 1 10 100 1k FREQUENCY - Hz 10k 100k 1M -Vs +0.0 0 5 10 15 SUPPLY VOLTAGE Volts 20 Figure 13. Negative PSR vs. Frequency Figure 16. Input Voltage Range vs. Supply Voltage 1000 +Vs -0.0 OUTPUT VOLTAGE SWING - Volts (REFERRED TO SUPPLY VOLTAGES) -0.5 -1.0 -1.5 R L= 10k CLOSED-LOOP GAIN - V/V 100 R L= 2k 10 +1.5 +1.0 +0.5 R L= 2k 1 R L= 10k 5 10 SUPPLY VOLTAGE Volts 15 20 0.1 100 -Vs +0.0 1k 10k 100k FREQUENCY - Hz 1M 10M 0 Figure 14. Closed-Loop Gain vs. Frequency Figure 17. Output Voltage Swing vs. Supply Voltage, G = 10 REV. A -7- AD621 30 5V OUTPUT VOLTAGE SWING - Volts p-p VS = 15V G = 10 20 100 90 1mV 10s 10 10 0% 0 0 100 1k LOAD RESISTANCE - 10k Figure 18. Output Voltage Swing vs. Resistive Load Figure 21. Large Signal Pulse Response and Settling Time, G = 100 (0.5 mV = 0.1%), RL = 2 k, CL = 100 pF 5V 100 90 1mV 10s 100 90 20mV 10s 10 0% 10 0% Figure 19. Large Signal Pulse Response and Settling Time Gain, G = 10 (0.5 mV = 0.01%), RL = 1 k , CL = 100 pF Figure 22. Small Signal Pulse Response, G = 100, RL = 2 k, CL = 100 pF 20 20mV 100 90 10s TO 0.01% 15 SETTLING TIME - s TO 0.1% 10 10 0% 5 0 0 5 10 15 20 OUTPUT STEP SIZE - Volts Figure 20. Small Signal Pulse Response, G = 10, RL = 1 k , CL = 100 pF Figure 23. Settling Time vs. Step Size, G = 10 -8- REV. A AD621 20 100V TO 0.01% 100 2V 15 SETTLING TIME - s 90 TO 0.1% 10 10 5 0% 0 0 5 10 15 20 OUTPUT STEP SIZE - Volts Figure 24. Settling Time vs. Step Size, Gain = 100 Figure 27. Gain Nonlinearity, G = 10, RL = 10 k, Vertical Scale: 100 V/Div = 100 ppm/Div, Horizontal Scale: 2 Volts/Div 2.0 1.5 +I B 1.0 INPUT CURRENT - nA 10k 1% INPUT 20V p-p 100k 0.1% 1k 10T 10k 1% VOUT 0.5 0 -0.5 -1.0 -I B G=10 G=100 11k 0.1% 1k 0.1% G=100 G=10 2 1 +VS 7 AD621 5 8 4 6 -1.5 -2.0 -125 3 -VS -75 -25 25 75 TEMPERATURE - C 125 175 Figure 25. Input Bias Current vs. Temperature Figure 28. Settling Time Test Circuit 0PW 0 100 90 VZR 0 100V 2V 10 0% 0 WFM 20 WFM AQR WARNING Figure 26. Gain Nonlinearity, G = 100, RL = 10 k, CL = 0 pF. Vertical Scale: 100 V/Div = 100 ppm/Div Horizontal Scale: 2 Volts/Div REV. A -9- AD621 +VS 7 I1 20A VB 20A I2 input voltage across the gain-setting resistor, RG, which equals R5 at a gain of 10 or the parallel combination of R5 and R6 at a gain of 100. This creates a differential gain from the inputs to the A1/A2 outputs given by G = (R1 + R2) / RG + 1. The unity-gain subtracter A3 removes any common-mode signal, yielding a singleended output referred to the REF pin potential. OUTPUT A3 6 10k REF Q2 R4 400 3 +IN 5 A1 C1 A2 C2 10k 10k R3 400 - IN 2 Q1 R1 25k R2 R5 5555.6 25k 10k R6 555.6 1 G=100 8 G=100 4 -VS Figure 29. Simplified Schematic of AD621 THEORY OF OPERATION The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gain-related errors. (b) The gain-bandwidth product (determined by C1, C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nV/Hz, determined mainly by the collector current and base resistance of the input devices. Make vs. Buy: A Typical Bridge Application Error Budget The AD621 is a monolithic instrumentation amplifier based on a modification of the classic three op amp circuit. Careful layout of the chip, with particular attention to thermal symmetry builds in tight matching and tracking of critical components, thus preserving the high level of performance inherent in this circuit, at a low price. On chip gain resistors are pretrimmed for gains of 10 and 100. The AD621 is preset to a gain of 10. A single external jumper (between Pins 1 and 8) is all that is needed to select a gain of 100. Special design techniques assure a low gain TC of 5 ppm/C max, even at a gain of 100. Figure 29 is a simplified schematic of the AD621. The input transistors Q1 and Q2 provide a single differential-pair bipolar input for high precision, yet offer 10x lower Input Bias Current, thanks to Supereta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1 and Q2, thereby impressing the +10V The AD621 offers improved performance over discrete three op amp IA designs, along with smaller size, fewer components and 10 times lower supply current. In the typical application, shown in Figure 30, a gain of 100 is required to amplify a bridge output of 20 mV full scale over the industrial temperature range of -40C to +85C. The error budget table below shows how to calculate the effect various error sources have on circuit accuracy. Regardless of the system it is being used in, the AD621 provides greater accuracy, and at low power and price. In simple systems, absolute accuracy and drift errors are by far the most significant contributors to error. In more complex systems with an intelligent processor, an auto-gain/auto-zero cycle will remove all absolute accuracy and drift errors leaving only the resolution errors of gain nonlinearity and noise, thus allowing full 14-bit accuracy. Note that for the discrete circuit, the OP07 specifications for input voltage offset and noise have been multiplied by 2. This is because a three op amp type in amp has two op amps at its inputs, both contributing to the overall input error. 10k* 10k* OP07D R = 350 R = 350 10k** AD621A R = 350 R = 350 REFERENCE 100** 10k** OP07D OP07D 10k* AD621A MONOLITHIC INSTRUMENTATION AMPLIFIER, G=100 SUPPLY CURRENT = 1.3mA MAX 10k* PRECISION BRIDGE TRANSDUCER 3 OP-AMP IN-AMP, G=100 *0.02% RESISTOR MATCH, 3PPM/C TRACKING **DISCRETE 1% RESISTOR, 100PPM/C TRACKING SUPPLY CURRENT = 15mA MAX Figure 30. Make vs. Buy -10- REV. A AD621 +5V 3k 3k 3 8 7 20k REF AD621B 3k 3k 1 2 4 5 6 10k IN ADC 20k DIGITAL DATA OUTPUT AD705 0.6mA MAX AGND 1.7mA 1.3mA MAX 0.10mA Figure 31. A Pressure Monitor Circuit which Operates on a +5 V Power Supply Pressure Measurement Although useful in many bridge applications such as weighscales, the AD621 is especially suited for higher resistance pressure sensors powered at lower voltages where small size and low power become more even significant. Figure 31 shows a 3 k pressure transducer bridge powered from +5 V. In such a circuit, the bridge consumes only 1.7 mA. Adding the AD621 and a buffered voltage divider allows the signal to be conditioned for only 3.8 mA of total supply current. Small size and low cost make the AD621 especially attractive for voltage output pressure transducers. Since it delivers low noise and drift, it will also serve applications such as diagnostic noninvasion blood pressure measurement. Wide Dynamic Range Gain Block Suppresses Large CommonMode and Offset Signals The AD621 is especially useful in wide dynamic range applications such as those requiring the amplification of signals in the presence of large, unwanted common-mode signals or offsets. Many monolithic in amps achieve low total input drift and noise errors only at relatively high gains (~100). In contrast the AD621's low output errors allow such performance at a gain of 10, thus allowing larger input signals and therefore greater dynamic range. The circuit of Figure 32 ( 15 V supply, G = 10) has only 2.5 V/C max. VOS drift and 0.55 /V p-p typical 0.1 Hz to 10 Hz noise, yet will amplify a 0.5 V differential signal while suppressing a 10 V common-mode signal, or it will amplify a 1.25 V differential signal while suppressing a 1 V offset by use of the DAC driving the reference pin of the AD621. An added benefit, the offsetting DAC connected to the reference pin allows removal of a dc signal without the associated time-constant of ac coupling. Note the representations of a differential and common-mode signal shown in Figure 32 such that a single-ended (or normal mode) signal of +1 V would be composed of a +0.5 V common-mode component and a +1 V differential component. Table I. Make vs. Buy Error Budget AD621 Circuit Calculation 125 V/20 mV N/A 2 nA x 350 /20 mV 110 dB3.16 ppm, x 5 V/20 mV Discrete Circuit Calculation (150 V x 2/20 mV ((150 V x 2)/100)/20 mV (6 nA x 350 )/20 mV (0.02% Match x 5 V)/20 mV Total Absolute Error DRIFT TO +85C Gain Drift, ppm/C Input Offset Voltage Drift, V/C Output Offset Voltage Drift, V/C 5 ppm x 60C 1 V/C x 60C/20 mV N/A 100 ppm/C Track x 60C (2.5 V/C x 2 x 60C)/20 mV (2.5 V/C x 2 x 60C)/100/20 mV Total Drift Error RESOLUTION Gain Nonlinearity, ppm of Full Scale 40 ppm Typ 0.1 Hz-10 Hz Voltage Noise, V p-p 0.28 V p-p/20 mV 40 ppm (0.38 V p-p x 2)120 mV Total Resolution Error Grand Total Error G = 100, VS = 15 V. (All errors are min/max and referred to input.) Error Source ABSOLUTE ACCURACY at TA = +25C Input Offset Voltage, V Output Offset Voltage, V Input Offset Current, nA CMR, dB Error, ppm of Full Scale AD621 Discrete 16,250 N/A 12,118 12,791 17,558 13,300 13,000 N/A 13,690 12,140 121,14 121,54 11,472 15,000 12,150 121,53 14,988 20,191 12,600 15,000 12,150 15,750 12,140 12,127 121,67 36,008 REV. A -11- AD621 INPUT A: 10V CM + VDIFF 0.5V + VCOM 10V- - Optional 2 1 8 3 x10 AD621 5 VOUT1 6 10k 2 1 8 3 G = 10 x10 AD621 5 VOUT2 6 INPUT B: 1V OFFSET + VDIFF + V OFFSET (1.25V + 1V) 0 TO 10V DAC 10k TOTAL GAIN = 100 - Use this in place of the DAC for zero suppression function. TO REF TO VOUT1 C R 2 6 AD548 3 Figure 32. Suppressing a Large Common-Mode or Offset Voltage in Order to Measure a Small Differential Signal (VS = 15 V) The AD621, as well as many other monolithic instrumentation amplifiers, is based on the "three op amp" in amp circuit (Figure 33) amplifier. Since the input amplifiers (A1 and A2) have a common-mode gain of unity and a differential gain equal to the set gain of the overall in amp, the voltages V1 and V2 are defined by the equations V1 = VCM + G x VDIFF/2 V2 = VCM - G x VDIFF/2 The common-mode voltage will drive the outputs of amplifiers A1 and A2 to the differential-signal voltage, multiplied by the gain, spreads them apart. For a +10 V common-mode +0.1 V differential input, V1 would be at +10.5 V and V2 at +9.5 V. INPUT AMPLIFIER DIFFERENTIAL GAIN = 10 COMMON MODE GAIN = 1 OUTPUT AMPLIFIER DIFFERENTIAL GAIN = 1 COMMON MODE GAIN = 1/1000 The AD621's input amplifiers can provide output voltage within 2.5 V of the supplies. To avoid saturation of the input amplifier the input voltage must therefore obey the equations: VCM + G x VDIFF/2 (Upper Supply - 2.5 V) VCM - G x VDIFF/2 (Lower Supply + 2.5 V) Figure 34 shows the trade-off between common-mode and differential-mode input for 15 V supplies and G = 10. By cascading with use of the optional AD621, the circuit of Figure 32 will provide 1 V of zero suppression at gains of 10 and 100 (at VOUT1 and VOUT2 respectively) with maximum TCs of 4 ppm/C and 8 ppm/C, respectively. Therefore, depending on the magnitude of the differential input signal, either VOUT1 or VOUT2 may be used as the output. 1.2 1.0 0.8 0.6 0.4 0.2 V1 10k 10k A1 4.44k 20k A3 10k A2 V2 10k Figure 33. Typical Three Op Amp Instrumentation Amplifier, Differential Gain = 10 VDIFF - Volts 20k 0 0 2 4 6 8 VCM - Volts 10 12 Figure 34. Trade-Off Between VCM and VDIFF Range (VS = 15 V, G = 10), for Reference Pin at Ground -12- REV. A AD621 Precision V-I Converter INPUT OVERLOAD CONSIDERATIONS The AD621 along with another op amp and two resistors make a precision current source (Figure 35). The op amp buffers the reference terminal to maintain good CMR. The output voltage VX of the AD621 appears across R1 which converts it to a current. This current less only the input bias current of the op amp then flows out to the load. +VS VIN+ 7 + Vx - Failure of a transducer, faults on input lines, or power supply sequencing can subject the inputs of an instrumentation amplifier to voltages well beyond their linear range, or even the supply voltage, so it is essential that the amplifier handle these overloads without being damaged. The AD621 will safely withstand continuous input overloads of 3.0 volts ( 6.0 mA). This is true for gains of 10 and 100, with power on or off. The inputs of the AD621 are protected by high current capacity dielectrically isolated 400 thin-film resistors R3 and R4 (Figure 29) and by diodes which protect the input transistors Q1 and Q2 from reverse breakdown. If reverse breakdown occurred, there would be a permanent increase in the amplifier's input current. The input overload capability of the AD621 can be easily increased while only slightly degrading the noise, common-mode rejection and offset drift of the device by adding external resistors in series with the amplifier's inputs as shown in Figure 36. Table II summarizes the overload voltages and total input noise for a range of range of r values. Note that a 2 k resistor in series with each input will protect the AD621 from a 15 volt continuous overload, while only increasing input noise to 13 nVHz--about the same level as would be expected from a typical unprotected 3 op amp in amp. Table II. Input Overload Protection vs. Value of Resistor RP 3 AD621 5 VIN- 2 4 -VS Vx R1 (VIN+ ) - (VIN- ) G R1 6 R1 IL AD705 I L= = LOAD Figure 35. Precision Voltage to Current Converter (Operates on 1.8 mA, 3 V) INPUT AND OUTPUT OFFSET VOLTAGE The AD621 is fully specified for total input errors at gains of 10 and 100. That is, effects of all error sources within the AD621 are properly included in the guaranteed input error specs, eliminating the need for separate error calculation. Total Error RTI = Input Error + (Output Error/G) Total Error RTO = (Input Error x G) + Output Error REFERENCE TERMINAL Total Input Noise Value of in nVHz @ 1 kHz Resistor RP G = 10 G = 100 0 499 1.00 k 2.00 k 3.01 k* 4.99 k* 14 14 14 15 16 17 9 10 11 13 14 16 Maximum Continuous Overload Voltage, VOL In Volts 3 6 9 15 21 33 Although usually grounded, the reference terminal may be used to offset the output of the AD621. This is useful when the load is "floating" or does not share a ground with the rest of the system. It also provides a direct means of injecting a precise offset. Another benefit of having a reference terminal is that it can be quite effective in eliminating ground loops and noise in a circuit or system. +VS *1/4 watt, 1% metal-film resistor. All others are 1/8 watt, 1% RN55 or equivalent. RP 2 VOL 7 VOUT AD621 VOL RP 3 GAIN = 10 OR 100 -VS 4 5 6 Figure 36. Input Overload Protection REV. A -13- AD621 Gain Selection +VS +VS 0.1F 2 7 10 The AD621 has accurate, low temperature coefficient (TC), gains of 10 and 100 available. The gain of the AD621 is nominally set at 10; this is easily changed to a gain of 100 by simply connecting a jumper between Pins 1 and 8. 2 555.5 REXT 5,555.5 - INPUTS 0.1F AD621 3 5 4 6 3 8 + OUTPUT 9 AD526 5 4 2 7 6 ... AD621 6 0.1F G = 10 -VS 0.1F 20k OFFSET NULL (OPTIONAL) ... 3 5 -VS Figure 38. A High Performance Programmable Gain Amplifier Figure 37. Programming the AD621 for Gains Between 10 and 100 COMMON-MODE REJECTION As shown in Figure 37, the device can be programmed for any gain between 10 and 100 by connecting a single external resistor between Pins 1 and 8. Note that adding the external resistor will degrade both the gain accuracy and gain TC. Since the gain equation of the AD621 yields: 9 (RX + 6,111.111) G = 1+ (RX + 555.555) Instrumentation amplifiers like the AD621 offer high CMR which is a measure of the change in output voltage when both inputs arc changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. For optimal CMR the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. In many applications shielded cables are used to minimize noise, and for best CMR over frequency the shield should he properly driven. Figures 39 and 40 show active data guards which are configured to improve ac common-mode rejections by "bootstrapping" the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. +VS - INPUT 2 7 1 100k VOUT This can be solved for the nominal value of external resistor for gains between 10 and 100: RX = (G - 1) 555.555 - 55,000 (10 - G ) Table III gives practical 1% resistor values for several common gains. Table III. Practical 1% External Resistor Values for Gains Between 10 and 100 Desired Recommended Gain 1% Resistor Value 10 20 50 100 (Pins 1 and 8 Open) 4.42 k 698 0 (Pins 1 and 8 Shorted)* Gain Error Temperature Coefficient (TC) * 10% 10% *5 ppm/C max 0.4 (50 ppm/C + Resistor TC) 0.4 (50 ppm/C + Resistor TC) *5 ppm/C max AD648 100 AD621 100 100k -VS 5 8 4 + INPUT 3 -VS 6 REFERENCE Figure 39. Differential Shield Driver, G = 10 +VS - INPUT 2 1 100 7 VOUT 6 5 4 REFERENCE A High Performance Programmable Gain Amplifier The excellent performance of the AD621 at a gain of 10 make it a good choice to team up with the AD526 programmable gain amplifier (PGA) to yield a differential input PGA with gains of 10, 20, 40, 80, 160. As shown in Figure 38, the low offset of the AD621 allows total circuit offset to be trimmed using the offset null of the AD526, with only a negligible increase in total drift error. The total gain TC will be 9 ppm/C max, with 2 V/C typical input offset drift. Bandwidth is 600 kHz to gains of 10 to 80, and 350 kHz at G = 160. Settling time is 13 s to 0.01% for a 10 V output step for all gains. AD548 8 + INPUT 3 AD621 -VS Figure 40. Common-Mode Shield Driver, G = 100 -14- REV. A AD621 GROUNDING +VS - INPUT 2 7 VOUT Since the AD621 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the REF pin to the appropriate "local ground." In order to isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (Figure 41). It would be convenient to use a single ground line; however, current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be tied together at some point, usually best at the ADC package as shown. ANALOG P.S. +15V C -15V AD621 5 4 3 + INPUT -VS 6 LOAD REFERENCE TO POWER SUPPLY GROUND DIGITAL P.S. C +5V Figure 42b. Ground Returns for Bias Currents when Using a Thermocouple Input +VS - INPUT 0.1F 0.1F 1F 1F 1F 2 7 VOUT 7 2 4 11 6 6 4 + 7 9 11 15 1 AD621 3 5 AD585 S/H AD621 DIGITAL DATA OUTPUT 6 5 AD574A ADC 4 + INPUT 3 REFERENCE -VS LOAD Figure 41. Basic Grounding Practice GROUND RETURNS FOR INPUT BIAS CURRENTS 100k 100k Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents; therefore when amplifying "floating" input sources such as transformers, or ac-coupled sources, there must be a dc path from each input to ground as shown in Figures 42a through 42c. Refer to the Instrumentation Amplifier Application Guide (free from Analog Devices) for more information regarding in amp applications. +VS - INPUT 2 7 VOUT TO POWER SUPPLY GROUND Figure 42c. Ground Returns for Bias Currents when Using AC Input Coupling AD621 5 4 + INPUT 3 -VS 6 LOAD REFERENCE TO POWER SUPPLY GROUND Figure 42a. Ground Returns for Bias Currents when Using Transformer Input Coupling REV. A -15- AD621 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-8) Package 8 5 1 4 0.39 (9.91) MAX 0.165 0.01 (4.19 0.25) SEATING PLANE 0.125 (3.18) MIN 0.18 0.03 (4.57 0.76) 0.035 0.01 (0.89 0.25) 0.30 (7.62) REF 0.011 0.003 (4.57 0.76) 0.018 0.003 (0.46 0.08) 0.033 (0.84) NOM 0.10 (2.54) TYP 0 - 15 Cerdip (Q-8) Package 0.005 (0.13) MIN 0.055 (1.4) MAX 8 5 0.310 (7.87) 0.220 (5.59) 1 4 0.070 (1.78) 0.030 (0.76) 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.150 (3.81) MIN 0.015 (0.38) 0.008 (0.20) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0 - 15 SEATING PLANE SOIC (R-8) Package 0.198 (5.03) 0.188 (4.77) 8 5 0.158 (4.00) 1 4 0.244 (6.200) 0.228 (5.80) 0.050 (1.27) TYP 0.018 (0.46) 0.014 (0.36) 0.205 (5.20) 0.181 (4.60) 0.010 (0.25) 0.004 (0.10) 0.094(2.39) 0.100 (2.59) 0.015 (0.38) 0.007 (0.18) 0.045 (1.15) 0.020 (0.50) -16- REV. A PRINTED IN U.S.A. 0.150 (3.80) C1673-24-6/92 0.25 (6.35) 0.31 (7.87) |
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